Publications of Eisenreich, H

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2 publication entries, 2 of them (printed in bold in the list) acknowledge the project support.

Paper (reviewed)

Scholze et al. 2011Scholze, S., Eisenreich, H., Höppner, S., Ellguth, G., Henker, S., Ander, M., Hänzsche, S., Partzsch, J., Mayr, C. and Schüffny, R.A 32 GBit/s communication SoC for a waferscale neuromorphic systemIntegration, the VLSI Journal (Elsevier) (2011) 45(1): 61-75,
Scholze et al. 2011bScholze, S., Schiefer, S., Partzsch, J., Hartmann, S., Mayr, C., Höppner, S., Eisenreich, H., Henker, S., Vogginger, B. and Schüffny, R.VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionalityFrontiers in Neuromorphic Engineering (2011) 5:117


26 August 2016